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An adaptive timing-driven placement for high performance VLSIs

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3 Author(s)
Sutanthavibul, S. ; Intel Corp., Hillsboro, OR, USA ; Shragowitz, E. ; Rung-Bin Lin

An application of constructive successive augmentation methodology to VLSI placement under constraints on routability, area and timing is described. To improve effectiveness of decision making, the placement algorithm uses adaptive and look-ahead procedures. This methodology was implemented in the placer-router JUNE for macrocell-library-based sea-of-gates design style with over-the-cell routing. JUNE achieves high utilization of area and timing requirements for real-life designs

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:12 ,  Issue: 10 )