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FAMOS: an efficient scheduling algorithm for high-level synthesis

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2 Author(s)
I. -C. Park ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; C. -M. Kyung

FAMOS, an iterative improvement scheduling algorithm for the high-level synthesis of digital systems, is described. The algorithm is based on a move acceptance strategy and various selection functions defined to represent the cost of hardware resources such as functional units and registers. A main feature of the algorithm is that it can escape from local minima. The algorithm can deal with diverse design styles such as multi-cycle operations, chained operations, pipelined datapaths, pipelined functional units and conditional branches. Register costs and maximal time constraints are also considered. To efficiently represent information on the design styles, a graph model called weighted precedence graph is proposed as a general model on which the scheduling algorithm is based. Despite the iterative nature, the proposed algorithm has a polynomial time complexity. Although the optimality of the algorithm is not guaranteed, optimal solutions were obtained for several examples available from the literature

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:12 ,  Issue: 10 )