Scheduled System Maintenance:
On May 6th, system maintenance will take place from 8:00 AM - 12:00 PM ET (12:00 - 16:00 UTC). During this time, there may be intermittent impact on performance. We apologize for the inconvenience.
By Topic

A 30 MHz FASTBUS transient digitizer data compactor using CMOS gate arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
1 Author(s)
Daviel, A. ; TRIUMF, Vancouver, BC, Canada

A 16-channel data compactor for the BNL 787 experiment is described. The module is designed to compact data from a 16-channel 256-bin 500-MHz charge coupled device (CCD) transient digitizer. Each channel accepts 8-b digitized data from a CCD module, performs pedestal subtraction and spike and zero-suppression, and formats the data together with channel identifiers into 32-b words for readout by FASTBUS. Data compaction is performed on-the-fly at a 30-MHz rate, with a 600-ns initial delay. Data for all channels may be read out in one FASTBUS block transfer operation. The module incorporates a fully featured FASTBUS slave interface built using a CMOS gate array (the PCL) and two bipolar gate arrays (ADIs)

Published in:

Nuclear Science, IEEE Transactions on  (Volume:40 ,  Issue: 4 )