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MONO/POLY technology for fabricating low-capacitance CMOS integrated circuits

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2 Author(s)
Ipri, A.C. ; David Sarnoff Res. Center, Princeton, NJ, USA ; Jastrzebski, L.L.

A process for the fabrication of CMOS transistors with oxide-isolated source-drain regions that are coplanar with the device channel region is described. The process uses the epitaxial lateral overgrowth technique to selectively grow single-crystal silicon from seed regions that will become the transistor channel regions. The source-drain regions are polycrystalline silicon and are deposited following the selective growth. n- and p-channel device characteristics are presented

Published in:

Electron Devices, IEEE Transactions on  (Volume:35 ,  Issue: 8 )

Date of Publication:

Aug 1988

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