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Optimizing real-time fault tolerance design in WSI

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1 Author(s)
J. R. Samson ; Honeywell Inc., Clearwater, FL, USA

An overview of real-time fault tolerance performance issues is provided, and a systematic approach to the optimization of real-time fault tolerance design in VLSI and wafer scale architectures is described and illustrated. The approach is based on the identification of fundamental optimization metrics, represented by simple product and quotient (reciprocal product) relationships, which extend traditional cost/benefit analysis to real-time fault tolerance in VLSI and wafer scale architectures and systems.

Published in:

Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on

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