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Effect of communication delay on gracefully degradable WSI processor array performance

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2 Author(s)
D. L. Landis ; Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA ; N. Nigam

Online reconfiguration of wafer scale integration (WSI) processor arrays provides graceful degradation of performance in the presence of failed processors. Each time a processor fails, soft switching can be used to bypass either a row or column and a degraded performance functional array can be maintained. Processor to processor communication delay may increase with each processor failure, and the entire array will eventually fail if the delay exceeds a predetermined limit. The impact of reconfiguration on fault tolerant WSI processor array performance is examined. The analysis considers interconnect length, communication delay, and maximum operating frequency.

Published in:

Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on

Date of Conference:

1993