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Two approaches for testing constant-geometry wafer scale integration (WSI) array architectures used in the computation of the complex N-point fast Fourier transform (FFT) under a single combinational fault model are presented. Initially, an unrestricted single cell-level fault model is considered. The first approach is based on a process whose complexity is independent of the number of cells in the FFT architecture. The second method is based on a testing process whose complexity is linear with respect to the number of stages (columns) of the FFT array. No additional hardware is required in this case. A component-level fault model is also proposed and analyzed.