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Three dimensional hybrid wafer scale integration using the GE high density interconnect technology

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4 Author(s)
Wojnarowski, R.J. ; Gen. Electr. Co., Schenectady, NY, USA ; Fillion, R.A. ; Gorowitz, B. ; Saia, R.

A three-dimensional multichip technology is discussed. It provides solutions to the interconnect and packaging problems associated with very high density requirements of large distributed processing systems and large solid-state memory systems. The technical approach involves an extension of the 2D multichip module (MCM) circuits fabricated with the high-density-interconnect (HDI) overlay technology. These are then stacked and interconnected with a modified version of the 2D HDI interconnect process applied to the side edges of the stack. Test structures and a stack of function circuit circuits are fabricated and tested. The features of this approach, a description of the process, and the results of tests on the demonstration vehicles are presented.

Published in:

Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on

Date of Conference:

1993

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