By Topic

A method for characterizing a microprocessor's vulnerability to SEU

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Elder, J.H. ; Aerospace Corp., Los Angeles, CA, USA ; Osborn, J. ; Kolasinski, W.A. ; Koga, R.

A system has been developed that tests microprocessors for single-event upset (SEU) at the specified clock speed and without adding wait or hold states. This system compiles a detailed record of SEU-induced errors and has been used to test the Sandia SA3000 microprocessor and prototypes of its commercial equivalent, the Harris H80C85 at the Lawrence Berkeley Laboratory 88-inch cyclotron facility. Using appropriate test programs and analyzing the resulting upset data, the authors have established the SEU cross section of the major functional elements of the hardened processors. With these cross sections and the estimated duty factors of a `typical' program, they computed the expected upset rate in a parallel, normally incident, beam as a function of linear energy transfer and measured the rate in several cyclotron beams. Good agreement between the measured and calculated rates was obtained

Published in:

Nuclear Science, IEEE Transactions on  (Volume:35 ,  Issue: 6 )