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High-level test generation for VLSI

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3 Author(s)
Bhattacharya, D. ; Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA ; Murray, B.T. ; Hayes, J.P.

The authors survey high-level approaches to test generation for VLSI circuits, which can significantly reduce test generation time while still providing good fault coverage. High-level approaches view the circuit with less structural detail, that is, from a more abstract viewpoint and often hierarchically. The authors first review some basic circuit and fault models and the two most widely known test-generation algorithms as a basis for comparison between high-level and low-level techniques. The authors then examine the more important high-level approaches, which fall into two broad classes, namely algorithmic and heuristic.<>

Published in:

Computer  (Volume:22 ,  Issue: 4 )