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Analog VLSI neural network implementations of hardware annealing and winner-take-all functions

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3 Author(s)
Joongho Choi ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Sheu, B.J. ; Gowda, S.M.

Hardware annealing and winner-take-all (WTA) functions have been implemented in 2.0-μm technology. The hardware annealing technique has been demonstrated using a 4×4 synapse network. Measurement results of a new WTA circuit are presented. The WTA circuit uses transistors biased in saturation to achieve high-speed performance. Since the comparison among the inputs is performed on one common signal line, the circuit can be easily extended to a larger dimension with that common signal line connected throughout the entire circuit. The new high-speed analog winner-take-all circuit can be extended linearly to at least 1024 inputs

Published in:

Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on

Date of Conference:

14-17 May 1991

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