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VLSI design of a massively parallel processor

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4 Author(s)
S. M. Karabernou ; IMAG/LGI, Grenoble, France ; G. Mazare ; E. Payan ; P. Rubini

Presents a massively parallel architecture whose goal is to take the best of today's VLSI capabilities. It is implemented as a 2-D grid of asynchronous cells communicating by message transfers with an overall MIMD (multiple-instruction-multiple-data) control. The elementary cell has two parts: a simple 8-bit processor plus local memory and a hardware-based communication mechanism. After introducing the global structure of this architecture, the communication problems, and approach to solving them, the authors focus on the basic cell by presenting the specificity of the processor and its associated communication mechanism. The whole cell VLSI design is presented

Published in:

Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on

Date of Conference:

14-17 May 1991