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Capacitance of top leads metal - comparison between formula, simulation, and experiment

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2 Author(s)
Wright, P.J. ; Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA ; Shih, Y.-C.A.

The parasitic interconnection capacitance can significantly degrade the performance of an IC. In this paper, the parasitic capacitance of the top leads with a protective overcoat (PO) dielectric is modeled. For a nitride only PO, the nitride increases the line-to-line capacitance component by the average of the nitride and underlying oxide dielectric constants with a maximum error of 11% according to two-dimensional numerical simulations. If the oxide thickness of the PO is greater than 0.2 μm, then the line-to-ground component of capacitance will be within 10% of the value of a lead surrounded by oxide. The line-to-line component of capacitance can have an error of over 30% and a modification is required to reduce the error. Two modifications for the nitride/oxide PO are given; both increase the line-to-line capacitance by the fraction of nitride between the leads. The results of the modifications and simulation are compared to experiment. The two-dimensional simulations and formulas have a good fit to the experimental data

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:12 ,  Issue: 12 )