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Electrical resistance as a limiting factor for high performance computer packaging

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1 Author(s)
A. Masaki ; Hitachi, Ltd., Tokyo, Japan

A formula is derived for the estimation of the packaging performance limit caused by wire resistance. This is applicable to the evaluation of the usefulness of high-temperature superconductors for improving computer packaging performance. The theoretical limit of wire delay caused by resistance is estimated to be several picoseconds from the case studies carried out using the formula.<>

Published in:

IEEE Circuits and Devices Magazine  (Volume:5 ,  Issue: 3 )