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A study of the use of local interconnect in CMOS leaf cell design

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2 Author(s)
Bachelu, C. ; Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada ; Lefebvre, M.

A leaf-cell layout methodology for harnessing the potential of the local interconnect (LI) layer in digital CMOS circuits is presented. Based on the line-of-diffusion layout style, LI is used for selected connections, typically at the output of logic gates, in order to free up the metal-one layer in congested areas. Experimental results based on a variety of logic cells which demonstrate the benefit of the LI in terms of cell area and routing flexibility are presented. Simulation results indicate that this benefit is without any detrimental effect on electrical performance.<>

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:1 ,  Issue: 4 )