Referenced Items are not available for this document.
The task of mapping a nested loop algorithm onto a multidimensional systolic array is considered. A buffer structure for the processing elements (PEs) that allows the data tokens to arrive at the PE earlier than when they are needed is proposed. Necessary and sufficient conditions for valid mappings using this buffer structure are then given. A refinement technique for deriving efficient statement level mappings from iteration level mappings is then proposed.<
Published in:
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
(Volume:1
,
Issue:
4
)
Date of Publication: Dec. 1993
- Page(s):
- 562 - 566
- ISSN :
- 1063-8210
- INSPEC Accession Number:
- 4634945
- Digital Object Identifier :
- 10.1109/92.250204
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Dec. 1993
- Sponsored by :
- IEEE Circuits and Systems Society
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