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Accurate computation of field reject ratio based on fault latency

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3 Author(s)
D. Das ; Cadence Design Systems, Noida, India ; S. C. Seth ; V. D. Agrawal

It is shown that the known methods of field reject ratio prediction are not accurate since they fail to realistically model the process of testing. The authors model the detection of a fault by an input test vector as a random event. However, the detection of a fault may be delayed for various reasons: the fault may be detectable only by application of a sequence of vectors or it may not have been targeted until later. In the statistical model, a fault is characterized by two parameters: a per-vector detection probability and an integer-valued latency. Irrespective of the detection probability, the fault cannot be detected by a vector sequence shorter than its latency. The circuit is characterized by the joint distribution of latency and detection probability over all faults. This distribution, obtained by applying the Bayes' rule to the actual test data, allows computations the field reject ratio. The sensitivity of this approach to variations in the measured parameters is also investigated.<>

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:1 ,  Issue: 4 )