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Greedy hardware optimization for linear digital circuits using number splitting and refactorization

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3 Author(s)
A. Chatterjee ; Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; R. K. Roy ; M. A. d'Abreu

A greedy optimization technique for minimizing the area of linear digital systems using a combination of common subexpression elimination and modification of multiplier coefficients is proposed. Since the amount of logic required by a coefficient multiplier is dependent on the value of the coefficient, the given system is transformed, using splitting of coefficients, in such a way that the overall circuit requires a smaller area. The approach explores a much larger design space as compared to previously known techniques. The approach is the first to optimize numerically intensive digital circuits by additive decomposition of multiplier coefficients. The new synthesis scheme generates functionally equivalent but structurally different circuits with a 15 to 40% reduction in area over conventional methods, for practical circuits with DSP applications.<>

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:1 ,  Issue: 4 )