Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

VLSI architectures for polygon recognition

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Sastry, R. ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA ; Ranganathan, N. ; Bunke, H.

A class of VLSI architectures is proposed for the computationally intensive task of polygon recognition in 3-D space. They make use of a set of local shape descriptors for polygons that are invariant under affine transformations. The recognition procedure is based on the matching of edge length ratios using a simplified version of the dynamic programming procedure commonly used for string matching. The matching procedure also copes with partial occlusion of polygons. The architectures are systolic and fully utilize the principles of pipelining and parallelism in order to obtain high speed and throughput. A prototype VLSI chip implementing one of the proposed architectures is currently being built.<>

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:1 ,  Issue: 4 )