Cart (Loading....) | Create Account
Close category search window
 

Implementations of smart pixels for optoelectronic processors and interconnection systems. II. SEED-based technology and comparison with optoelectronic gates

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Song Yu ; Dept. of Electr. Eng., Princeton Univ., NJ, USA ; Forrset, S.R.

For part I see ibid., vol. 11, no. 10, pp. 1659-1669 (Oct. 1993). In part I, the authors discussed the optoelectronic approach to the implementation of smart pixels for optical interconnection and optical computing systems. In this second paper, a similar analysis is done for SEED-based technologies. The technologies investigated include the symmetric SEED (S-SEED), asymmetric Fabry-Perot (ASFP) SEED, shallow quantum well SEED, and FET-SEED. Of these technologies, it is found that FET-SEED (whose structure is closely similar to optoelectronic logic gates) has the highest sensitivity and operates at the highest bandwidth. The advantages and limitations of the two approaches are compared, considering such system performance issues as the maximum information flux density, temperature sensitivity, and optical coupling efficiency. It is concluded that the optoelectronic approach is useful in applications which require high bandwidth (>1 GHz), complex logic functions, and moderate pixel density, while the SEED-based approach is more suitable to high-density interconnections used at moderate bandwidths (<100 MHz). Furthermore, the maximum information flux density of 2-D optoelectronic and FET-SEED logic gates is approximately 200 GHz/cm2, which is from 1 to 2 orders of magnitude larger than for other SEED-based array technologies

Published in:

Lightwave Technology, Journal of  (Volume:11 ,  Issue: 10 )

Date of Publication:

Oct 1993

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.