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Boundary walking test: an accelerated scan method for greater system reliability

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1 Author(s)
J. C. Chan ; IBM Corp., Austin, TX, USA

Printed circuit board (PCB) interconnect test and reliability is addressed. The boundary scan test methodology proposed in the IEEE standard 1149.1 is reviewed, and its limitation is critically analyzed. Based on this, a technique is proposed to automate the interconnect wiring test, which is performed as part of the power-on self-test. Essential to the idea is the use of a walking sequence for test stimulus, and response compression by the multiple input signature registers (MISRs). The salient feature is its simplicity of operation. Unlike the existing boundary-scan methodology, interconnects are tested via on-site test generation; faults are detected by comparing the content of the MISR with the anticipated response. Formal analysis shows that the technique has a high test-coverage for the most common defects. As a result, PCB interconnect testing can be accomplished as part of the power-on self-test without external test fixtures

Published in:

IEEE Transactions on Reliability  (Volume:41 ,  Issue: 4 )