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An analytical back gate bias dependent threshold voltage model for SiGe-channel ultrathin SOI PMOS devices

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3 Author(s)
Kuo, J.B. ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Mao-Chuan Tang ; Jai-Hoon Sim

An analytical threshold voltage model for SiGe-channel ultrathin SOI PMOS devices is presented. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical-formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide

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Electron Devices, IEEE Transactions on  (Volume:40 ,  Issue: 12 )