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PIAF: efficient IC floor planning

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2 Author(s)
M. A. Jabri ; Sch. of Electr. Eng., Sydney Univ., NSW, Australia ; D. J. Skellern

The authors present a method for selecting an efficient rectangular topology for IC floor plans. PIAF's floor-planning strategy separates generation and testing, which greatly reduces solution space and confines domain knowledge. Consequently, they have exploited concepts of functional and physical design representation to extract domain knowledge. The authors introduce and discuss IC design-tool limitations. PIAF's structure, its floor-planning strategy, implementations of its KBS tasks, and its context structure are regarded as unique. The authors conclude that although PIAF is still experimental, its good results prove that IC floor planning is a successful application domain for knowledge-based programming techniques.<>

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IEEE Expert  (Volume:4 ,  Issue: 2 )