Cart (Loading....) | Create Account
Close category search window
 

On integrating control algorithms for buffer management and concurrency for parallel transaction processing systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Shiwei Wang ; Aiken Comput. Lab., Harvard Univ., Boston, MA, USA ; Hsu, Y.

The performance of multi-processor based data sharing complex for transaction processing can be enhanced through the use of an integrated concurrency-coherency-recovery protocol. This protocol, combined with the use of shared main memory buffer, can allow early commit of transaction updates, reduce multi-system coupling overhead, and eliminate the unnecessary disk updates in transaction processing in normal time. Results obtained from performance simulation study show a significant improvement in the maximum transaction throughput can be sustained if this integrated protocol is used

Published in:

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Date of Conference:

22-24 May 1991

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.