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On integrating control algorithms for buffer management and concurrency for parallel transaction processing systems

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2 Author(s)
Shiwei Wang ; Aiken Comput. Lab., Harvard Univ., Boston, MA, USA ; Hsu, Y.

The performance of multi-processor based data sharing complex for transaction processing can be enhanced through the use of an integrated concurrency-coherency-recovery protocol. This protocol, combined with the use of shared main memory buffer, can allow early commit of transaction updates, reduce multi-system coupling overhead, and eliminate the unnecessary disk updates in transaction processing in normal time. Results obtained from performance simulation study show a significant improvement in the maximum transaction throughput can be sustained if this integrated protocol is used

Published in:

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Date of Conference:

22-24 May 1991