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The designs of two-level pipelined systolic arrays for recursive digital filters with maximum throughput rate

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3 Author(s)
Shih-Chieh Wen ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chi-Min Liu ; Chein-Wei Jen

Presents two-level pipelined systolic arrays for high throughput IIR filters. By combining the look-ahead schemes and the two-level pipelining technique, the VLSI architectures which support the maximum throughput rate and the strategies which make this rate possible are derived. Extending the results concluded from 1-D IIR filters, the authors also present high throughput rate realizations for 2-D IIR filters

Published in:

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Date of Conference:

22-24 May 1991