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New methods for parallel pattern fast fault simulation for synchronous sequential circuits

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2 Author(s)
M. Mojtahedi ; Duisburg Univ., Germany ; W. Geisselhardt

The authors present COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED is based on coupling a parallel pattern simulator with a non-parallel simulator. COMBINED runs substantialy faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator

Published in:

European Test Conference, 1993. Proceedings of ETC 93., Third

Date of Conference:

19-22 Apr 1993