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System clock estimation based on clock slack minimization

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2 Author(s)
Narayan, S. ; Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA ; Gajski, D.D.

When estimating a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Traditional high-level synthesis systems require the designer to specify the clock cycle explicitly or express operator delays in terms of multiples of a clock cycle. The authors present an algorithm for clock estimation from dataflow graphs, based on clock slack minimization. This will provide both designers and synthesis tools with a realistic estimate of the clock cycle that can be used to implement a design. By using real life components and examples, it is shown that the clock estimates produced by this method yield faster execution times for the designs, as compared to the maximum operator delay methods. It is observed that the designs scheduled with the clock cycle estimates have faster execution times regardless of the components finally allocated for implementing the design during synthesis

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992