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DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits

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3 Author(s)
Agrawal, P. ; AT&T Bell Lab., Murray Hill, NJ, USA ; Agrawal, V.D. ; Seth, S.C.

The authors provide a method of finding all sensitizable paths in a non-scan synchronous sequential circuit. Path activation conditions of the circuit are mapped onto a single stuck type fault by adding a few modeling gates to the netlist. The path is considered to be sensitizable only if the corresponding stuck type fault is found detectable by a sequential circuit test generator. A depth-first analysis of circuit topology that determines all paths between primary inputs, primary outputs and flip-flops employs a partial path hierarchy. All paths with a common unsensitizable segment need not be examined separately. Results on benchmark circuits show that: (1) the number of sensitizable paths can be significantly smaller than that found by a static timing analyzer, and (2) the partial path analysis adds to efficiency when the number of sensitizable paths is less than 20%

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992