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ALU synthesis from HDL descriptions to optimized multi-level logic

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1 Author(s)
Buijs, F. ; Cadlab, Paderborn, Germany

The author presents a new tool for automatic ALU (arithmetic and logic unit) synthesis that combines the translation from an HDL to logic level and subsequent multi-level logic synthesis. The existing tools treat ALUs as random logic in that they neglect the regularity of ALUs. These tools do not achieve good results for ALUs. In contrast, the described tool partitions the ALU into blocks such as bit-slices, just as in manual designs. Comparisons with existing tools show significant improvement

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992