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Topology optimization techniques for power/ground networks in VLSI

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3 Author(s)
Erhard, K.-H. ; Corp. Res. & Dev., Siemens AG, Munich, Germany ; Johannes, F.M. ; Dachauer, R.

The authors present two methods for optimizing the topology of given power/ground networks on VLSI chips. The cycle-reduction-method removes cycles and root paths (paths between two pads) in a general power/ground graph. The node-reduction-method removes branching nodes (nodes incident to more than two branches) in a power/ground tree. Both methods yield a reduction of the power/ground routing area and do not degrade the reliability of the power/ground network. Small examples to explain the procedures are included and experimental results for benchmark circuits are presented

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992

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