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Linear time fault simulation algorithm using a content addressable memory

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2 Author(s)
N. Ishiura ; Dept. of Inf. Syst. Eng., Osaka Univ., Japan ; S. Yajima

The authors present a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The new algorithm attempts to reduce the computation time by processing many faults at a time on the assumption that a content addressable memory can be regarded as a single instruction multiple data (SIMD) type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is comparable to that of a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992