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Random current testing for CMOS logic circuits by monitoring a dynamic power supply current

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3 Author(s)
Tamamoto, H. ; Dept. of Inf. Eng., Akita Univ., Japan ; Yokoyama, H. ; Narita, Y.

Assuming a stuck-at type fault, the authors discuss current testing for CMOS logic circuits where the random patterns generated by a linear feedback shift register (LFSR) are applied, and a dynamic power supply current is monitored. The LFSR is modified such that there exists a feedback from the outputs of a circuit under test to the LSFR. This modification is intended for amplifying the effect of a fault near a primary output on the dynamic current. In order to distinguish the dynamic current of a faulty circuit from the one of a fault-free circuit, two methods are discussed. One is the method where the waveform of the dynamic current is recognized using a neural network, and the other is the method where the mean dynamic current is calculated. Simulation results show that a high fault coverage can be obtained using a small number of test vectors

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992

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