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Test generation for IDDQ testing and leakage fault detection in CMOS circuits

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3 Author(s)
Mahlstedt, U. ; Inst. fuer Theor. Elektrotecknik, Hannover Univ., Germany ; Heinitz, M. ; Alt, J.

The authors describe a two-stage method to generate test sets for quiescent power supply current, IDDQ, testing and to determine the leakage fault coverage for given test pattern sets. The method is integrated within a fault simulator. It is proved that any complete test pattern set generated for stuck-at faults detects all leakage faults caused by intra-gate shorts within a static CMOS circuit if the circuit contains only primitive gates (inverter, buffer, AND, NAND, OR, NOR)

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992