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Synthesis of VHDL arrays on RAM cells

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3 Author(s)
Berthet, C. ; Thomson Composants Militaires et Spatiaux, St-Egreve, France ; Rampon, J. ; Sponga, L.

The problem of array objects in VHSIC hardware description language (VHDL) specifications for synthesis is considered. Experience shows that circuits obtained by synthesis tools are not as efficient as RAM macrocells. A new synthesis method is proposed that consists in mapping a VHDL array to a RAM primitive, together with a modification of the specification. The primitive is then mapped to a RAM generator of the THOMSON-TMS CSAM Library

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992