Cart (Loading....) | Create Account
Close category search window
 

Using VHDL for datapath synthesis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Olive, V. ; Rance-Telecom, CNET-Grenoble, Meylan, France ; Airiau, R. ; Berge, J.M. ; Robert, A.

The authors present a VHSIC hardware description language (VHDL) interface for a datapath generator. It introduces a method which is specific as well as library management for simulating and making synthesis. Implementing the data-path layout is discussed, and the specific use of VHDL for building the circuit layout is described. The entire interface has been specified in VHDL, demonstrating the possibility of extending the semantics of VHDL by adding particular attributes

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.