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Challenges in the analysis of VHDL

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3 Author(s)
Bernstein, D.B. ; Vantage Anal. Syst. Inc., Fremont, CA, USA ; Charness, D. ; Farrow, R.

VHSIC hardware description language (VHDL) is a rich and complex formal language. Its many constructs allow for a wide description of hardware behavior. Many of the features, however, require semantics which are often difficult or expensive to properly analyze. The authors discuss several of these features, explaining why they exist, why they are hard to implement, and some strategies for easing their use

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992