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Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I and M

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1 Author(s)
S. Maginot ; LEDA SA, Meylan, France

VHSIC hardware description language (VHDL) is compared to three other well-known hardware description languages: Verilog (from Cadence Design Systems, now public), UDL/1 (new Japanese standards,) and M (from Mentor Graphics). This comparative study parallels the fundamental concepts of these languages and highlights the different design processes and methodologies they require. VHDL is a general-purpose modeling language, whereas Verilog, UDL/I and M are more dedicated to IC modeling. The predefined environment of VHDL compares poorly to the implicit IC environment of other languages

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992