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A family of parallel prefix algorithms embedded in networks

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1 Author(s)
M. Takesue ; NTT Software Res. Labs., Tokyo, Japan

This paper presents a family of algorithms for producing, from (υ0, υ1, ..., υn-1), all initial prefixes xi0θυ1 θ···θυi (i=0, 1, ..., n-1) in parallel in interconnection networks such as the omega network and the hypercube, where θ is an associative binary operator. Each algorithm can be embedded in the switches and interconnections of the network, and can be executed in O((log2 r+1) logr n) time steps provided that the network connecting n processors is constructed by using an r×r switch, and that parallelism within as well as among individual switches is exploited. The objective of these algorithms is to attain a communication pattern that fits the topology of the network. One type of network can be made equivalent to, or can be embedded in, another type of network, so a family of algorithms can be derived from one basic algorithm. In the basic algorithm, every processor pi upward multicasts υi to processors pk (k=i+1, i+2, ..., n - 1). En route to pi, υj (j=0, 1, ..., i - 1) are combined in the switches to produce the (i - 1)th initial prefix xi-1 that is received by pi, which can then compute the ith initial prefix xi=xi-1θυi

Published in:

IEEE Transactions on Parallel and Distributed Systems  (Volume:4 ,  Issue: 10 )