A family of parallel prefix algorithms embedded in networks

This paper presents a family of algorithms for producing, from ( upsilon /sub 0/, upsilon /sub 1/, ..., upsilon /sub n-1/), all initial prefixes x/sub i/= upsilon /sub 0/ theta upsilon /sub 1/ theta ... theta upsilon /sub i/ (i=0, 1, ..., n-1) in parallel in interconnection networks such as the omega network and the hypercube, where theta is an associative binary operator. Each algorithm can be embedded in the switches and interconnections of the network, and can be executed in O((log/sub 2/ r+1) log/sub r/ n) time steps provided that the network connecting n processors is constructed by using an r*r switch, and that parallelism within as well as among individual switches is exploited. The objective of these algorithms is to attain a communication pattern that fits the topology of the network. One type of network can be made equivalent to, or can be embedded in, another type of network, so a family of algorithms can be derived from one basic algorithm. In the basic algorithm, every processor p/sub i/ upward multicasts upsilon /sub i/ to processors p/sub k/ (k=i+1, i+2, ..., n - 1). En route to p/sub i/, upsilon /sub j/ (j=0, 1, ..., i - 1) are combined in the switches to produce the (i - 1)th initial prefix x/sub i-1/ that is received by p/sub i/, which can then compute the ith initial prefix x/sub i/=x/sub i-1/ theta upsilon /sub i/.<
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