Design of a self-reconfiguring interconnection network for fault-tolerant VLSI processor arrays

An interconnection network capable of spontaneously reconfiguring a VLSI processor array on detection of faulty processors is presented. Although the reconfiguration process is global, the network control circuitry is localized around each processor and is therefore completely modular. The structure of the control circuitry is fixed and thus independent of the array size or the number of spare processors. The network performance in yield enhancement is analyzed through Monte Carlo simulation. The network effectiveness in using surviving processors is close to that of an ideal network (one capable of tolerating as many faulty processors per row as there are spare processors per row). Strategies involved in testing the fault-tolerant array are also presented. Test circuitry is placed around each of the processors to enable testing of all the processors in parallel. The same circuitry is used to test the interconnection network efficiently. The additional silicon area requirements due to the network and the test circuitries are examined through the design of a prototype fault-tolerant array