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A 6-ns cycle 256-kb cache memory and memory management unit

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2 Author(s)
Heald, R.A. ; Adv. Processor Div., Intergraph Corp., Huntsville, AL, USA ; Holst, J.C.

A 6-ns cycle, 7.7-ns access cache memory and memory management unit (CAMMU) chip has been developed. The circuit includes two 5-ns 128-kb cache memories, two 4-ns 64-entry fully associative translation lookaside buffers (TLBs), two 4-ns 64-line tag RAMs, comparators, registers, and control logic. The TLB design contains a line encoder and valid bits with flash clear. Timing control allows read, write, associative accesses, and invalid search accesses with identical timings. The two caches time-share data input and sense amplifier circuits for improved density, and they are pipelined to allow a new access to start before the previous access is complete

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:28 ,  Issue: 11 )