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High-performance devices for a 0.15- mu m CMOS technology

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12 Author(s)
G. G. Shahidi ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; J. Warnock ; S. Fischer ; P. A. McFarland
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Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 mu m and minimum channel length below 0.1 mu m. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 mu m, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF/sub 2/ implant were used. Maximum high V/sub DS/ threshold rolloff was 250 mV at effective channel length of 0.06 mu m. For the minimum channel length of 0.1 mu m, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively.<>

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IEEE Electron Device Letters  (Volume:14 ,  Issue: 10 )