By Topic

A new approach to the problem of PLA partitioning using the theory of the principal lattice of partitions of a submodular function

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Roy, S. ; Indian Inst. of Technol., Bombay, India ; Narayanan, H.

An area efficient 2 level implementation of combinational logic can be achieved by partitioning the original PLA into several PLAs each of which interacts with the others weakly. A PLA implementing a sum of products logic functions can be modelled through a bipartite graph B G, which specifies the intersection of rows (minterms) with columns of the AND plane (primary inputs) and the OR plane (primary outputs) respectively. The authors show how to achieve a good PLA partition by using the principal lattice of partitions of the incidence function of BG

Published in:

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Date of Conference:

23-27 Sep 1991