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Partial silicon compilation of recursive digital filters using VHDL

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1 Author(s)
Junior, N.S. ; CPqD-Telebras, Campinas, Sao Paolo

The FOREST computer program for the functional and architectural synthesis of recursive digital filters is described. It outputs a bit-serial architecture in the form of a VHDL netlist that may be used as input of any available logic synthesis and layout tool that accepts VHDL

Published in:
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Date of Conference: 23-27 Sep 1991

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