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Clock tree synthesis for high performance ASICs

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1 Author(s)
Burkis, J. ; Motorola Inc., Chandler, AZ, USA

Using clock tree synthesis to create a high performance clocking network during layout requires the implementation of an active buffer distribution that is a design and technology specific trade-off between skew sensitivity, clock insertion delay, and simultaneously switching power dissipation

Published in:

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Date of Conference:

23-27 Sep 1991