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A new hierarchical approach to test-pattern generation

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2 Author(s)
E. C. Weening ; MESA Res. Inst., Twente Univ., Enschede, Netherlands ; H. G. Kerkhoff

The authors present a new and fully hierarchical approach to automatic test-pattern generation, for digital MOS VLSI circuits. The description of a VLSI circuit consists of several hierarchical levels of interconnected modules. Each module consists of one or more sub-modules are functionally described by ordered binary decision diagrams (OBDD). The OBDDs of its sub-modules, starting from the lowest-level modules. Test-patterns are generated for each module using previously generated test-patterns for its sub-modules, starting at the switch-level. Accurate fault models, like the line stuck-at and switch stuck-on/open models, are used to model physical defects. At higher levels, faults are modeled by the test-patterns covering the fault. Results on large combinatorial circuits confirm the feasibility of the new test-pattern generation approach, and its superiority over conventional non-hierarchical methods

Published in:

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Date of Conference:

23-27 Sep 1991