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FISTEM: a CAD tool for synthesis of easily testable FSM

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2 Author(s)
Prakash, B. ; Dept. of Electr. Eng., Indian Inst. of Technol., Kanpur, India ; Hasan, M.M.

In this paper the authors propose a new system named FISTEM for testability synthesis and test generation of PLA-based finite state machines. A nonscan design methodology, based on constrained state assignment and logic optimization, is used which guarantees testability for all combinationally irredundant crosspoint faults in the PLA. Test sequences for these faults are obtained using combinational test generation techniques alone. An exact algorithm is used for this to obtain maximum fault coverage. For different state machines considered, the system works very efficiently to produce an optimized easily testable PLA-based logic implementation with small overhead in area

Published in:

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Date of Conference:

23-27 Sep 1991