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CMOS multiple-valued logic design. I. Circuit implementation

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3 Author(s)
Jain, A.K. ; Dept. of Electr. Eng., Saskatchewan Univ., Saskatoon, Sask., Canada ; Bolton, R.J. ; Abd-El-Barr, M.H.

A CMOS circuit implementation of a functionally complete multiple-valued logic (MVL) set of operators is proposed. The set consists of literal, cycle, complement of literal, complement of cycle, min, and tsum operators. In all of the circuits, multiple-valued logic levels are represented in terms of current values. Binary voltage signals are generated inside the circuits using a threshold circuit element. These binary voltage signals are used to generate control signals for switches to realize appropriate current levels for the desired multiple-valued logic levels. Transient analysis simulations (using HSPICE) to verify the functionality of the designed circuits and the effect of variation in process parameters are also reported

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Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:40 ,  Issue: 8 )