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Designing high-performance processors using real address prediction

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3 Author(s)
Hua, K.A. ; Dept. of Comput. Sci., Central Florida Univ., Orlando, FL, USA ; Liu, L. ; Jih-Kwon Peir

The authors propose design techniques that may significantly simplify the cache access path, and hence offer the opportunity of shorter cycle time or fewer pipeline stages. Their proposals are based on highly accurate prediction methods that allow them to efficiently resolve address translation information early in the pipe

Published in:

Computers, IEEE Transactions on  (Volume:42 ,  Issue: 9 )